Live briefing
Everything about SystemC
C++ extensions for simulating embedded systems
SystemC is a set of C++ classes and macros which provide an event-driven simulation interface. These facilities enable a designer to simulate concurrent processes, each described using plain C++ syntax. SystemC processes can communicate in a simulated real-time environment, using signals of all the datatypes offered by C++, some additional ones offered by the SystemC library, as well as user defined. In certain respects, SystemC deliberately mimics the hardware description languages VHDL and Verilog, but is more aptly described as a system-level modeling language. Wikipedia →
🧭 Start here: a 6-step reading path
- Read the overview: SystemCA 5-minute orientation
- Skim a recent paper: SystemC-based Co-Simulation/Analysis for System-Level Hardware/Software Co-DesignInfluential work since 2022
- Pick up a classic book: A SystemC PrimerThe most-reprinted book on the subject
- Read the landmark paper: MPARM: Exploring the Multi-Processor SoC Design Space with SystemCCited 183 times
- Go sideways: Transaction-level modelingA closely related topic
- Go sideways: VHDLA closely related topic
📖 Definitions
No dictionary entry for this exact phrase.
🗂️ The subject at a glance
🏆 Landmark papers (most cited)
MPARM: Exploring the Multi-Processor SoC Design Space with SystemC
S2CBench: Synthesizable SystemC Benchmark Suite for High-Level Synthesis
Systemc cosimulation and emulation of multiprocessor soc designs
Design and verification of SystemC transaction-level models
A QEMU and SystemC-Based Cycle-Accurate ISS for Performance Estimation on SoC Development
Software Model Checking SystemC
A framework for heterogeneous specification and design of electronic embedded systems in SystemC
Verifying SystemC Using Intermediate Verification Language and Stateful Symbolic Simulation
🆕 Influential since 2022
SystemC-based Co-Simulation/Analysis for System-Level Hardware/Software Co-Design
Modeling Cyber-Physical Production Systems with SystemC-AMS
A Systematic Mapping Study on SystemC/TLM Modeling Capabilities in New Research Domains
Through the Looking Glass: Automated Design Understanding of SystemC-Based VPs at the ESL
A composite SystemC-UVM abstract optimal path selection verification architecture for complex designs
📚 Books worth reading
A SystemC PrimerJ. Bhasker · 2002
Digitale Hardware/Software-SystemeChristian Haubelt · 2010
Ranked by number of editions on Open Library, a rough measure of how lasting a book is.
🔗 Related topics
- Transaction-level modeling Transaction-level modeling (TLM) is an approach to modelling complex digital systems by using electronic design automation software. TLM is used primarily…
- VHDL VHDL (VHSIC hardware description language) is a hardware description language that can model the behavior and structure of digital systems at multiple…
- High-level verification High-level verification (HLV), or electronic system-level (ESL) verification, is the task to verify ESL designs at high abstraction level, i.e., it is…
- Catapult C Catapult C Synthesis, a commercial electronic design automation product of Mentor Graphics, is a high-level synthesis tool, sometimes called algorithmic…
- Verilog Verilog, standardized as IEEE 1364, is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design and…
- VHDL-AMS VHDL-AMS is a derivative of the hardware description language VHDL (IEEE 1076-2002). It includes analog and mixed-signal extensions (AMS) in order to define…
- Verilog-AMS Verilog-AMS is a derivative of the Verilog hardware description language that includes Analog and Mixed-Signal extensions (AMS) in order to define the…
- SystemVerilog SystemVerilog, standardized as IEEE 1800 by the Institute of Electrical and Electronics Engineers (IEEE), is a hardware description and hardware verification…