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Everything about High-level verification
Verifying task for ESL designs at high abstraction level
High-level verification (HLV), or electronic system-level (ESL) verification, is the task to verify ESL designs at high abstraction level, i.e., it is the task to verify a model that represents hardware above register-transfer level (RTL) abstract level. For high-level synthesis, HLV is to HLS as functional verification is to logic synthesis. Wikipedia →
🧭 Start here: a 6-step reading path
- Read the overview: High-level verificationA 5-minute orientation
- Skim a recent paper: High-Level Expression of Recombinant VHSV Glycoprotein Using Transformed C. vulgaris and Verification of Vaccine EfficacyInfluential work since 2022
- Pick up a classic book: Simple art of SoC designThe most-reprinted book on the subject
- Read the landmark paper: Kami: a platform for high-level parametric hardware specification and its modular verificationCited 94 times
- Go sideways: High-level synthesisA closely related topic
- Go sideways: Catapult CA closely related topic
📖 Definitions
No dictionary entry for this exact phrase.
🗂️ The subject at a glance
🏆 Landmark papers (most cited)
Kami: a platform for high-level parametric hardware specification and its modular verification
Formal verification of complex business processes based on high-level Petri nets
Speaker Verification Using Support Vector Machines and High-Level Features
An Equivalence-Checking Method for Scheduling Verification in High-Level Synthesis
Fuzzy rule base systems verification using high-level petri nets
High-level design verification of microprocessors via error modeling
Formal verification of high-level synthesis
Verification of Datapath and Controller Generation Phase in High-Level Synthesis of Digital Circuits
🆕 Influential since 2022
High-Level Expression of Recombinant VHSV Glycoprotein Using Transformed C. vulgaris and Verification of Vaccine Efficacy
EMSim: A Fast Layout Level Electromagnetic Emanation Simulation Framework for High Accuracy Pre-Silicon Verification
A Three-Pronged Verification Approach to Higher-Level Verification Using Graph Data Structures
Hardware IP watermarking and verification strategy in high level synthesis
Molecular dynamics simulation and thermodynamic calculation verification of nuclide separation from high-level radioactive waste liquids in supercritical water
📚 Books worth reading
Simple art of SoC designKeating, Michael · 2011
Ranked by number of editions on Open Library, a rough measure of how lasting a book is.
🔗 Related topics
- High-level synthesis High-level synthesis (HLS), sometimes referred to as C synthesis, electronic system-level (ESL) synthesis, algorithmic synthesis, or behavioral synthesis…
- Catapult C Catapult C Synthesis, a commercial electronic design automation product of Mentor Graphics, is a high-level synthesis tool, sometimes called algorithmic…
- C to HDL C to HDL tools convert C language or C-like source code into a hardware description language (HDL) such as VHDL or Verilog. The converted code can then…
- Logic synthesis In computer engineering, logic synthesis is a process by which an abstract specification of desired circuit behavior, typically at register transfer level…
- Hardware description language In computer engineering, a hardware description language (HDL) is a specialized computer language used to describe the structure and behavior of electronic…
- Forte Design Systems Forte Design Systems, Inc. was a San Jose, CA, based provider of high-level synthesis (HLS) software products, also known as electronic system-level (ESL)…
- Silicon compiler A silicon compiler is a specialized electronic design automation (EDA) tool that automates the process of creating an integrated circuit (IC) design from…
- Electronic system-level design and verification Electronic system level (ESL) design and verification is an electronic design methodology, focused on higher abstraction level concerns. The term Electronic…