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Everything about Directory-based cache coherence
Scalable coherence technique
In computer engineering, directory-based cache coherence is a type of cache coherence mechanism, where directories are used to manage caches in place of bus snooping. Bus snooping methods scale poorly due to the use of broadcasting. These methods can be used to target both performance and scalability of directory systems. Wikipedia →
🧭 Start here: a 6-step reading path
- Read the overview: Directory-based cache coherenceA 5-minute orientation
- Pick up a classic book: How to Write a Research PaperThe most-reprinted book on the subject
- Read the landmark paper: Directory-based cache coherence in large-scale multiprocessorsCited 165 times
- Go sideways: Directory-based coherenceA closely related topic
- Go sideways: Scalable Coherent InterfaceA closely related topic
📖 Definitions
No dictionary entry for this exact phrase.
🏆 Landmark papers (most cited)
Directory-based cache coherence in large-scale multiprocessors
The directory-based cache coherence protocol for the DASH multiprocessor
ADir/sub p/NB: a cost-effective way to implement full map directory-based cache coherence protocols
Correction to 'Directory-based cache coherence in large-scale multiprocessor'
Phase-Priority Based Directory Coherence for Multicore Processor
Directory-based cache coherence scheme using number-balanced binary tree
An innovative implementation for directory-based cache coherence in shared memory multiprocessors
📚 Books worth reading
How to Write a Research PaperSimon Kendal · 2015
How to Write a Research PaperSimon Kendal · 2013
How to Write a Research PaperSimon Kendal · 2013
How to Write a Research PaperSimon Kendal · 2013
Ranked by number of editions on Open Library, a rough measure of how lasting a book is.
🔗 Related topics
- Directory-based coherence Directory-based coherence is a mechanism to handle cache coherence problem in distributed shared memory (DSM) a.k.a. non-uniform memory access (NUMA).…
- Scalable Coherent Interface The Scalable Coherent Interface or Scalable Coherent Interconnect (SCI), is a high-speed interconnect standard for shared memory multiprocessing and message…
- Cache coherence In computer architecture, cache coherence is the uniformity of shared resource data that is stored in multiple local caches. In a cache coherent system…
- Distributed shared memory In computer science, distributed shared memory (DSM) is a form of memory architecture where physically separated memories can be addressed as a single…
- Bus snooping Bus snooping or bus sniffing is a scheme by which a coherency controller (snooper) in a cache (a snoopy cache) monitors or snoops the bus transactions…
- CPU cache A CPU cache is a hardware cache used by the central processing unit (CPU) of a computer to reduce the average cost (time or energy) to access data from…
- Unrolled linked list In computer programming, an unrolled linked list is a variation on the linked list which stores multiple elements in each node. It can dramatically increase…
- MESI protocol The MESI protocol is an invalidate-based cache coherence protocol, and is one of the most common protocols that support write-back caches. It is also known…