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Everything about Tomasulo's algorithm
Computer architecture hardware algorithm
Tomasulo's algorithm is a computer architecture hardware algorithm for dynamic scheduling of instructions that allows out-of-order execution and enables more efficient use of multiple execution units. It was developed by Robert Tomasulo at IBM in 1967 and was first implemented in the IBM System/360 Model 91's floating-point unit. Wikipedia →
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- Read the overview: Tomasulo's algorithmA 5-minute orientation
- Read the landmark paper: Android-based Simulator to Support Tomasulo Algorithm Teaching and LearningCited 1 times
- Go sideways: Reservation stationA closely related topic
- Go sideways: Out-of-order executionA closely related topic
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- Reservation station A unified reservation station, also known as unified scheduler, is a decentralized feature of the microarchitecture of a CPU that allows for register renaming…
- Out-of-order execution In computer engineering, out-of-order execution (or more formally dynamic execution) is an instruction scheduling paradigm used in high-performance central…
- Hazard (computer architecture) In the domain of central processing unit (CPU) design, hazards are problems with the instruction pipeline in CPU microarchitectures when the next instruction…
- Scoreboarding Scoreboarding is a centralized method, first used in the CDC 6600 computer, for dynamically scheduling instructions so that they can execute out of order…
- Register renaming In computer architecture, register renaming is a technique that abstracts logical registers from physical registers. Every logical register has a set of…
- Re-order buffer A re-order buffer (ROB) is a hardware unit used in an extension to Tomasulo's algorithm to support out-of-order and speculative instruction execution.…
- Transport triggered architecture In computer architecture, a transport triggered architecture (TTA) is a kind of processor design in which programs directly control the internal transport…
- Classic RISC pipeline In the history of computer hardware, some early reduced instruction set computer central processing units (RISC CPUs) used a very similar architectural…