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Everything about Register-transfer level
Digital circuit design abstraction
In digital circuit design, register-transfer level (RTL) is a design abstraction which models a synchronous digital circuit in terms of the flow of digital signals (data) between hardware registers, and the logical operations performed on those signals. Wikipedia →
🧭 Start here: a 6-step reading path
- Read the overview: Register-transfer levelA 5-minute orientation
- Skim a recent paper: Corrections to “GNN-Based Hardware Trojan Detection at Register Transfer Level Leveraging Multiple-Category Features”Influential work since 2022
- Pick up a classic book: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and SimulationThe most-reprinted book on the subject
- Read the landmark paper: Automated transformation of algorithms into register-transfer level implementationsCited 62 times
- Go sideways: Power optimization (EDA)A closely related topic
- Go sideways: Timing closureA closely related topic
📖 Definitions
No dictionary entry for this exact phrase.
🗂️ The subject at a glance
🏆 Landmark papers (most cited)
Automated transformation of algorithms into register-transfer level implementations
Power Side-Channel Leakage Assessment Framework at Register-Transfer Level
Automatic test pattern generation for functional register-transfer level circuits using assignment decision diagrams
Register transfer level power optimization with emphasis on glitch analysis and reduction
A design-for-testability technique for register-transfer level circuits using control/data flow extraction
TAO: regular expression-based register-transfer level testability analysis and optimization
Register-Transfer-Level Features for Machine-Learning-Based Hardware Trojan Detection
Detecting Unknown Hardware Trojans in Register Transfer Level Leveraging Verilog Conditional Branching Features
🆕 Influential since 2022
Corrections to “GNN-Based Hardware Trojan Detection at Register Transfer Level Leveraging Multiple-Category Features”
Design of DCO-OFDM System for VLC on Chip at the Register-Transfer Level
GNN-Based Hardware Trojan Detection at Register Transfer Level Leveraging Multiple-Category Features
Evaluating Large Language Models for Automatic Register Transfer Logic Generation for Combinational Circuits via High-Level Synthesis
Incremental Concolic Testing of Register-Transfer Level Designs
📚 Books worth reading
- 📕Integrated Circuit and System Design. Power and Timing Modeling, Optimization and SimulationJosé L. Ayala, Delong Shang · 2013
Ranked by number of editions on Open Library, a rough measure of how lasting a book is.
🔗 Related topics
- Power optimization (EDA) Power optimization is the use of electronic design automation tools to optimize (reduce) the power consumption of a digital design, such as that of an…
- Timing closure Timing closure in VLSI design and electronics engineering is the iterative design process of assuring all signals satisfy the timing requirements in a…
- Clock gating In computer architecture, clock gating is a popular power management technique used in many synchronous circuits for reducing dynamic power dissipation…
- Integrated circuit design Integrated circuit design, semiconductor design, chip design or IC design, is a sub-field of electronics engineering, encompassing the particular logic…
- Formal equivalence checking Formal equivalence checking process is a part of electronic design automation (EDA), commonly used during the development of digital integrated circuits…
- Logic simulation Logic simulation is the use of simulation software to predict the behavior of digital circuits and hardware description languages. Simulation can be performed…
- Design closure Design Closure is a part of the digital electronic design automation workflow by which an integrated circuit (i.e. VLSI) design is modified from its initial…
- Physical design (electronics) In integrated circuit design, physical design is a step in the standard design cycle which follows after the circuit design. At this step, circuit representatio…