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Everything about Clock gating
Power management technique for synchronous digital circuits
In computer architecture, clock gating is a popular power management technique used in many synchronous circuits for reducing dynamic power dissipation, by removing the clock signal when the circuit, or a subpart of it, is idle. Clock gating saves power by pruning part of the clock tree distribution, at the cost of adding more logic to a circuit. Wikipedia →
🧭 Start here: a 6-step reading path
- Read the overview: Clock gatingA 5-minute orientation
- Skim a recent paper: Design and evaluation of clock-gating-based approximate multiplier for error-tolerant applicationsInfluential work since 2022
- Pick up a classic book: Woodworking projects 1990 yearbook.The most-reprinted book on the subject
- Read the landmark paper: Ultra Low-Power Clocking Scheme Using Energy Recovery and Clock GatingCited 107 times
- Go sideways: Logic familyA closely related topic
- Go sideways: Low power flip-flopA closely related topic
📖 Definitions
No dictionary entry for this exact phrase.
🗂️ The subject at a glance
🏆 Landmark papers (most cited)
Ultra Low-Power Clocking Scheme Using Energy Recovery and Clock Gating
Circadian clock-dependent gating in ABA signalling networks
Value-based clock gating and operation packing
DCG: deterministic clock-gating for low-power microprocessor design
Power Reduction by Clock Gating Technique
Clock-Gating of Streaming Applications for Energy Efficient Implementations on FPGAs
Reduction of Noise Using Continuously Changing Variable Clock and Clock Gating for IC Chips
Harmonic Rejection Mixing Techniques Using Clock-Gating
🆕 Influential since 2022
Design and evaluation of clock-gating-based approximate multiplier for error-tolerant applications
A Novel Clock Gating Approach for the Design of Low-Power Linear Feedback Shift Registers
Fully Automated Hardware-Driven Clock-Gating Architecture With Complete Clock Coverage for 4 nm Exynos Mobile SOC
Hybrid Data Driven Clock Gating and Data Gating Technique for Better Saving Power in ALU RISC-V
Detection of Malicious Threats Exploiting Clock-Gating Hardware Using Machine Learning
📚 Books worth reading
Woodworking projects 1990 yearbook.Ranked by number of editions on Open Library, a rough measure of how lasting a book is.
🔗 Related topics
- Logic family In computer engineering, a logic family is one of two related concepts: A logic family of monolithic digital integrated circuit devices is a group of electronic…
- Low power flip-flop Low power flip-flops are flip-flops that are designed for low-power electronics, such as smartphones and notebooks. A flip-flop, or latch, is a circuit…
- Clock signal In electronics and especially synchronous digital circuits, a clock signal (historically also known as logic beat) is an electronic logic signal (voltage…
- State encoding for low power State encoding assigns a unique pattern of ones and zeros to each defined state of a finite-state machine (FSM). Traditionally, design criteria for FSM…
- Low-power electronics Low-power electronics are electronics designed to consume less electrical power than usual, often at some expense. For example, notebook processors usually…
- Power gating Power gating is a technique used in integrated circuit design to reduce power consumption, by shutting off the current to blocks of the circuit that are…
- Register-transfer level In digital circuit design, register-transfer level (RTL) is a design abstraction which models a synchronous digital circuit in terms of the flow of digital…
- Low-power FSM synthesis Finite-state machines (FSMs) are widely used to implement control logic in various applications such as microprocessors, digital transmission, digital…