Live briefing
Everything about RISC-V
Open-source CPU instruction set architecture
RISC-V is a free and open standard instruction set architecture (ISA) for computer CPUs. It is based on reduced instruction set computer (RISC) principles. Unlike proprietary ISAs such as x86 and ARM, RISC-V is described as "free and open" because its specifications are released under permissive open-source licenses and can be implemented without paying royalties. Wikipedia →
🧭 Start here: a 6-step reading path
- Read the overview: RISC-VA 5-minute orientation
- Skim a recent paper: Life of RISC: Formation, action, and degradation of RNA-induced silencing complexInfluential work since 2022
- Pick up a classic book: The RISC-V ReaderThe most-reprinted book on the subject
- Read the landmark paper: Development of a new resilience scale: The Connor-Davidson Resilience Scale (CD-RISC)Cited 9,742 times
- Go sideways: OpenRISCA closely related topic
- Go sideways: ARM architecture familyA closely related topic
📖 Definitions
No dictionary entry for this exact phrase.
🗂️ The subject at a glance
🏆 Landmark papers (most cited)
Development of a new resilience scale: The Connor-Davidson Resilience Scale (CD-RISC)
Psychometric analysis and refinement of the connor–davidson resilience scale (CD‐RISC): Validation of a 10‐item measure of resilience
Human RISC Couples MicroRNA Biogenesis and Posttranscriptional Gene Silencing
Crystal Structure of Argonaute and Its Implications for RISC Slicer Activity
FACTOR ANALYSIS AND PSYCHOMETRIC EVALUATION OF THE CONNOR-DAVIDSON RESILIENCE SCALE (CD-RISC) WITH CHINESE PEOPLE
Purified Argonaute2 and an siRNA form recombinant human RISC
Argonaute2 Cleaves the Anti-Guide Strand of siRNA during RISC Activation
An abbreviated version of the Connor-Davidson Resilience Scale (CD-RISC), the CD-RISC2: Psychometric properties and applications in psychopharmacological trials
🆕 Influential since 2022
Life of RISC: Formation, action, and degradation of RNA-induced silencing complex
RISC-V Instruction Set Architecture Extensions: A Survey
A Boron, Nitrogen, and Oxygen Doped π‐Extended Helical Pure Blue Multiresonant Thermally Activated Delayed Fluorescent Emitter for Organic Light Emitting Diodes That Shows Fast k RISC Without the Use of Heavy Atoms
A RISC-V 32-bit microprocessor based on two-dimensional semiconductors
A High-Performance Domain-Specific Processor With Matrix Extension of RISC-V for Module-LWE Applications
📚 Books worth reading
The RISC-V ReaderDavid A. Patterson, Andrew Waterman · 2017
Ranked by number of editions on Open Library, a rough measure of how lasting a book is.
🔗 Related topics
- OpenRISC OpenRISC is a project to develop a series of open-source hardware based central processing units (CPUs) on established reduced instruction set computer…
- ARM architecture family ARM (stylised in lowercase as arm) is a family of RISC instruction set architectures for computer processors. Arm Holdings develops the instruction set…
- Instruction set architecture An instruction set architecture (ISA) is an abstract model that defines the programmable interface of the CPU of a computer, defining how software interacts…
- Bit manipulation instructions Bit manipulation instructions are instructions that perform bit manipulation operations in hardware, rather than requiring several instructions for those…
- SuperH SuperH (or SH) is a 32-bit reduced instruction set computing (RISC) instruction set architecture (ISA) developed by Hitachi and currently produced by Renesas…
- MIPS architecture MIPS (Microprocessor without Interlocked Pipelined Stages) is a family of reduced instruction set computer (RISC) instruction set architectures (ISA) developed…
- History of general-purpose CPUs The history of general-purpose CPUs is a continuation of the earlier history of computing hardware. In the early 1950s, each computer design was unique…
- Intel i960 Intel's i960 (or 80960) is a RISC-based microprocessor design that became popular during the early 1990s as an embedded microcontroller. It became a best-sellin…