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Everything about Memory access pattern
In computing, a memory access pattern or IO access pattern is the pattern with which a system or program reads and writes memory on secondary storage. These patterns differ in the level of locality of reference and drastically affect cache performance, and also have implications for the approach to parallelism and distribution of workload in shared memory systems. Further, cache coherency issues can affect multiprocessor performance, which means that certain memory access patterns place a ceiling on parallelism. Wikipedia →
🧭 Start here: a 6-step reading path
- Read the overview: Memory access patternA 5-minute orientation
- Skim a recent paper: Near-Optimal Multirun March Memory Test Algorithms for Neighborhood Pattern-Sensitive Faults in Random-Access MemoriesInfluential work since 2022
- Pick up a classic book: Photonics for processors, neural networks, and memoriesThe most-reprinted book on the subject
- Read the landmark paper: Highly-Efficient Hardware Architecture for CRYSTALS-Kyber With a Novel Conflict-Free Memory Access PatternCited 53 times
- Go sideways: Parallel RAMA closely related topic
- Go sideways: Cache prefetchingA closely related topic
📖 Definitions
No dictionary entry for this exact phrase.
🗂️ The subject at a glance
🏆 Landmark papers (most cited)
Highly-Efficient Hardware Architecture for CRYSTALS-Kyber With a Novel Conflict-Free Memory Access Pattern
Rethinking Parallel Memory Access Pattern in Number Theoretic Transform Design
New Strategy to Access Dual‐Stimuli‐Responsive Triple‐Shape‐Memory Effect in a Non‐overlapping Pattern
Fast Access and Low Memory Star Pair Catalog for Star Pattern Identification
NeuroTAP: Thermal and Memory Access Pattern-Aware Data Mapping on 3D DRAM for Maximizing DNN Performance
Access pattern restructuring for memory energy
A Lightweight Memory Access Pattern Obfuscation Framework for NVM
Access pattern-based memory and connectivity architecture exploration
🆕 Influential since 2022
📚 Books worth reading
Photonics for processors, neural networks, and memoriesJoseph L. Horner · 1993
Ranked by number of editions on Open Library, a rough measure of how lasting a book is.
🔗 Related topics
- Parallel RAM In computer science, a parallel random-access machine (parallel RAM or PRAM) is a shared-memory abstract machine. As its name indicates, the PRAM is intended…
- Cache prefetching Cache prefetching is a technique used by central processing units (CPUs) to boost execution performance by fetching instructions or data from their primary…
- General-purpose computing on graphics processing units General-purpose computing on graphics processing units (GPGPU, or less often GPGP) is the use of a graphics processing unit (GPU), which typically handles…
- Linearizability In concurrent programming, an operation (or set of operations) is linearizable if it consists of an ordered list of invocation and response events, that…
- Concurrent hash table A concurrent hash table or concurrent hash map is an implementation of hash tables allowing concurrent access by multiple threads using a hash function…
- Gather/scatter Gather/scatter is a type of memory addressing that at once collects (gathers) from, or stores (scatters) data to, multiple arbitrary memory indices. Examples…
- Oblivious RAM An Oblivious RAM (ORAM) simulator is a compiler that transforms an algorithm in such a way that the resulting algorithm preserves the input-output behavior…
- Write buffer A write buffer is a type of data buffer that can be used to hold data being written from the cache to main memory or to the next cache in the memory hierarchy…