Everything about Latency oriented processor architecture
Microprocessor microarchitecture
Latency oriented processor architecture is the microarchitecture of a microprocessor designed to serve a serial computing thread with a low latency. This is typical of most central processing units (CPU) being developed since the 1970s. These architectures, in general, aim to execute as many instructions as possible belonging to a single serial thread, in a given window of time; however, the time to execute a single instruction completely from fetch to retire stages may vary from a few cycles to even a few hundred cycles in some cases. Latency oriented processor architectures are the opposite of throughput-oriented processors which concern themselves more with the total throughput of the system, rather than the service latencies for all individual threads that they work on. Wikipedia →
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- Read the overview: Latency oriented processor architectureA 5-minute orientation
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- Go sideways: MicroarchitectureA closely related topic
- Go sideways: Classic RISC pipelineA closely related topic
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đź“š Books worth reading
Programming Massively Parallel ProcessorsDavid Kirk, Wen-Mei W. Hwu · 2010
Advances in Computing, Communication, and ControlSrija Unnikrishnan · 2013
Ranked by number of editions on Open Library, a rough measure of how lasting a book is.
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