Everything about Inter-processor interrupt
Type of interrupt signal sent between computer processors
In computing, an inter-processor interrupt (IPI), also known as a shoulder tap, is a special type of interrupt by which one processor may interrupt another processor in a multiprocessor system if the interrupting processor requires action from the other processor. Actions that might be requested include:Flush memory management unit caches, such as translation lookaside buffers, on other processors when memory mappings are changed by one processor; Stop when the system is being shut down by one processor. Notify an alternate CPU of a malfunction for Alternate CPU Recovery (ACR). Notify a processor that higher-priority work is available. Notify a processor of work that cannot be done on all processors due to, e.g., asymmetric access to I/O channels special features on some processors Wikipedia →
🧠Start here: a 6-step reading path
- Read the overview: Inter-processor interruptA 5-minute orientation
- Pick up a classic book: Architecture of Computing Systems – ARCS 2013The most-reprinted book on the subject
- Read the landmark paper: Interrupt processing in concurrent processorsCited 24 times
- Go sideways: Advanced Programmable Interrupt ControllerA closely related topic
- Go sideways: Symmetric multiprocessingA closely related topic
đź“– Definitions
No dictionary entry for this exact phrase.
🏆 Landmark papers (most cited)
Interrupt processing in concurrent processors
A method of processor selection for interrupt handling in a multiprocessor system
Improving the Performances of the nMPRA Processor using a Custom Interrupt Management Scheduling Policy
An Implementation of Task Switching and Interrupt Handling Mechanisms of OSEK Operating System based on ARM Processor
Test environment for verification of multi-processor interrupt system with virtualization support
Microprocessor interrupt handling
đź“š Books worth reading
Architecture of Computing Systems – ARCS 2013Hana Kubátová · 2013
Introduction to embedded systemsDavid James Russell · 2010
Ranked by number of editions on Open Library, a rough measure of how lasting a book is.
đź”— Related topics
- Advanced Programmable Interrupt Controller The Advanced Programmable Interrupt Controller (APIC) is a family of programmable interrupt controllers developed by Intel. As its name suggests, the APIC…
- Symmetric multiprocessing Symmetric multiprocessing or shared-memory multiprocessing (SMP) involves a multiprocessor computer hardware and software architecture where two or more…
- Interrupt In digital computers, an interrupt is a request for the processor to interrupt currently executing code (when permitted), so that the event can be processed…
- Channel I/O In computing, channel I/O is a high-performance input/output (I/O) architecture that is implemented in various forms on a number of computer architectures…
- Multiprocessing Multiprocessing (MP) is the use of two or more central processing units (CPUs) within one computer system. The term also refers to the ability of a system…
- Multiprocessor system architecture A multiprocessor (MP) system is defined as "a system with more than one processor", and, more precisely, "a number of central processing units linked together…
- Task Control Block The Task Control Block (TCB) is a data structure which contains the state of a task in, e.g., OS/360 and successors on IBM System/360 architecture and…
- Asymmetric multiprocessing An asymmetric multiprocessing (AMP or ASMP) system is a multiprocessor computer system where not all of the multiple interconnected central processing…