Live briefing
Everything about DLX
RISC processor architecture
The DLX is a RISC processor architecture designed by John L. Hennessy and David A. Patterson, the principal designers of the Stanford MIPS and the Berkeley RISC designs (respectively), the two benchmark examples of RISC design. Wikipedia →
🧠Start here: a 6-step reading path
- Read the overview: DLXA 5-minute orientation
- Skim a recent paper: DLX genes and proteins in mammalian forebrain developmentInfluential work since 2022
- Pick up a classic book: DLX BXThe most-reprinted book on the subject
- Read the landmark paper: Interneuron Migration from Basal Forebrain to Neocortex: Dependence on Dlx GenesCited 1,304 times
- Go sideways: Classic RISC pipelineA closely related topic
- Go sideways: Instruction set architectureA closely related topic
đź“– Definitions
Symbol Symbol for decilux, an SI unit of illumination equal to 10 lux.
🗂️ The subject at a glance
🏆 Landmark papers (most cited)
Interneuron Migration from Basal Forebrain to Neocortex: Dependence on Dlx Genes
The Evf-2 noncoding RNA is transcribed from the Dlx-5/6 ultraconserved region and functions as a Dlx-2 transcriptional coactivator
Pallial and subpallial derivatives in the embryonic chick and mouse telencephalon, traced by the expression of the genes Dlx-2, Emx-1, Nkx-2.1, Pax-6, and Tbr-1
Spatially restricted expression of Dlx-1, Dlx-2 (Tes-1), Gbx-2, and Wnt- 3 in the embryonic day 12.5 mouse forebrain defines potential transverse and longitudinal segmental boundaries
Mutations of the Homeobox Genes Dlx-1 and Dlx-2 Disrupt the Striatal Subventricular Zone and Differentiation of Late Born Striatal Neurons
Developmental functions of theDistal-less/Dlx homeobox genes
Specification of Jaw Subdivisions by Dlx Genes
Role of the Dlx Homeobox Genes in Proximodistal Patterning of the Branchial Arches: Mutations of Dlx-1, Dlx-2, and Dlx-1 and -2 Alter Morphogenesis of Proximal Skeletal and Soft Tissue Structures Derived from the First and Second Arches
🆕 Influential since 2022
DLX genes and proteins in mammalian forebrain development
DLX Genes in the Development and Maintenance of the Vertebrate Skeleton: Implications for Human Pathologies
Dual Leadership in the Matrix: Effects of Leader-Member Exchange (LMX) and Dual-Leader Exchange (DLX) on Role Conflict and Dual Leadership Effectiveness
DLX gene expression in the developing chick pharyngeal arches and relationship to endothelin signaling and avian jaw patterning
14. Preclinical Pharmacology of DLX-001, a Novel Non-Hallucinogenic Neuroplastogen With the Potential for Treating Neuropsychiatric Diseases
đź“š Books worth reading
DLX BXPeter Pauper · 2007
DLX BOXPeter Pauper · 2007
The DLX instruction set architecture handbookPhilip M. Sailer · 1996- 📕Grimms Fairy Tls DlxGebrüder Grimm [Brothers Grimm] · 1945
Deluxe Parish Bible - BurgundyDlx Parish · 1999- 📕Legendary Illustration Art of NC Wyeth DLXJ. David Spurlock, N. C. Wyeth · 2012
PAINTINGS OF J ALLEN ST JOHN DLXStephen D. Korshak, J. David Spurlock · 2009- 📕BRZRKR Deluxe EditionKeanu Reeves, Matt Kindt · 2024
Ranked by number of editions on Open Library, a rough measure of how lasting a book is.
đź”— Related topics
- Classic RISC pipeline In the history of computer hardware, some early reduced instruction set computer central processing units (RISC CPUs) used a very similar architectural…
- Instruction set architecture An instruction set architecture (ISA) is an abstract model that defines the programmable interface of the CPU of a computer, defining how software interacts…
- Instruction cycle The instruction cycle (also known as the fetch–decode–execute cycle, or simply the fetch–execute cycle) is the cycle that the central processing unit (CPU)…
- MIPS architecture MIPS (Microprocessor without Interlocked Pipelined Stages) is a family of reduced instruction set computer (RISC) instruction set architectures (ISA) developed…
- Reduced instruction set computer In electronics and computer science, a reduced instruction set computer (RISC, pronounced "risk") is a computer architecture designed to simplify the individual…
- Comparison of instruction set architectures An instruction set architecture (ISA) is an abstract model of a computer, also referred to as computer architecture. A realization of an ISA is called…
- Load–store architecture In computer engineering, a load–store architecture (or a register–register architecture) is an instruction set architecture that divides instructions into…
- Stanford MIPS MIPS (also known as Stanford MIPS to disambiguate it from later architectures), an acronym for Microprocessor without Interlocked Pipeline Stages, was…