Everything about Compute Express Link
Open standard processor interconnection for data centers
Compute Express Link (CXL) is an open standard interconnect for high-speed, high capacity CPU-to-device and CPU-to-memory connections, designed for high performance data center computers. CXL is built on the serial PCI Express (PCIe) physical and electrical interface and includes PCIe-based block input/output protocol (CXL.io) and new cache-coherent protocols for accessing system memory (CXL.cache) and device memory (CXL.mem). The serial communication and pooling capabilities allows CXL memory to overcome performance and socket packaging limitations of common DIMM memory when implementing high storage capacities. Wikipedia →
🧭 Start here: a 6-step reading path
- Read the overview: Compute Express LinkA 5-minute orientation
- Skim a recent paper: Compute Express Link Topology-Aware and Expander-Driven Prefetching: Unlocking Solid-State Drive PerformanceInfluential work since 2022
- Pick up a classic book: Fundamentals of Computer Programming with CSharp Free Book (by Nakov & Co.)The most-reprinted book on the subject
- Read the landmark paper: An Introduction to the Compute Express Link (CXL) InterconnectCited 138 times
- Go sideways: Coherent Accelerator Processor InterfaceA closely related topic
- Go sideways: Gen-Z (consortium)A closely related topic
📖 Definitions
No dictionary entry for this exact phrase.
🗂️ The subject at a glance
🏆 Landmark papers (most cited)
An Introduction to the Compute Express Link (CXL) Interconnect
Compute Express Link (CXL): Enabling Heterogeneous Data-Centric Computing With Heterogeneous Memory Hierarchy
Improving Key-Value Cache Performance With Heterogeneous Memory Tiering: A Case Study of Compute-Express-Link-Based Memory Expansion
Novel Composable and Scaleout Architectures Using Compute Express Link
CXL (Compute Express Link) Technology
Pipelined and Partitionable Forward Error Correction and Cyclic Redundancy Check Circuitry Implementation for PCI Express 6.0 and Compute Express Link 3.0
Improving SQL Join Algorithms for Distributed Systems: A Case Study of Compute Express Link-Based Multihost Shared Memory
AI-Driven Verification for Compute Express Link (CXL): Challenges, Innovations, and Future
🆕 Influential since 2022
Compute Express Link Topology-Aware and Expander-Driven Prefetching: Unlocking Solid-State Drive Performance
cPMEM: A Design of Byte-Addressable Persistent Memory with Compute Express Link for Data Center Applications
cPMEM: A Design of Byte-Addressable Persistent Memory with Compute Express Link for Data Center Applications
From Block to Byte: Transforming PCIe Solid-State Devices With Compute Express Link Memory Protocol and Instruction Annotation
📚 Books worth reading
Fundamentals of Computer Programming with CSharp Free Book (by Nakov & Co.)Svetlin Nakov · 2013
Ranked by number of editions on Open Library, a rough measure of how lasting a book is.
🔗 Related topics
- Coherent Accelerator Processor Interface Coherent Accelerator Processor Interface (CAPI), is a high-speed processor expansion bus standard for use in large data center computers, initially designed…
- Gen-Z (consortium) The Gen-Z Consortium was a trade group of technology vendors involved in designing CPUs, random access memory, servers, storage, and accelerators. The…
- UCIe Universal Chiplet Interconnect Express (UCIe) is an open specification for a die-to-die interconnect and serial bus between chiplets. It is co-developed…
- PCI Express PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe, is a high-speed standard used to connect hardware components inside…
- HyperTransport HyperTransport (HT), formerly known as Lightning Data Transport, is a technology for interconnection of computer processors. It is a bidirectional serial/parall…
- RapidIO RapidIO is a packet-switched interconnect technology used to link electronic components. It allows devices to exchange messages, perform read and write…
- Intel QuickPath Interconnect The Intel QuickPath Interconnect (QPI) is a scalable processor interconnect developed by Intel which replaced the front-side bus (FSB) in Xeon, Itanium…
- ARM Neoverse The ARM Neoverse is a group of 64-bit ARM processor cores licensed by Arm Holdings. The cores are intended for datacenter, edge computing, and high-performance…